module LCD_clk(clk50M,rst_n,LCD_clk);
input clk50M,rst_n;
output LCD_clk;
reg LCD_clk_r;
assign LCD_clk=LCD_clk_r;
reg [31:0] div_cnt;
always@(posedge clk50M or negedge rst_n)
begin
if(!rst_n)
begin
    LCD_clk_r<=1'b0;
    div_cnt<=0;
end
else
begin
   if(div_cnt>=49999)
   begin
       div_cnt<=0;
       LCD_clk_r<=~LCD_clk_r;
   end
   else
   begin
       div_cnt<=div_cnt+1;
   end
end
end
endmodule 